(a) Field of the Invention
This disclosure relates to a pixel array layout of a liquid crystal display.
(b) Description of the Related Art
A data driver for a liquid crystal display (“LCD”) is more expensive than a LCD gate driver, and it can be difficult to integrate a data driver on a glass substrate using an amorphous silicon (“a-Si”) thin film transistor (“TFT”) and provide a data driver having high mobility. In addition, a cost of a data driver can exponentially increase according to the number of channels in an LCD. Therefore it would be desirable to decrease the number of data driver and/or the number of gate driver channels to reduce manufacturing cost.
FIG. 1 is a schematic plan view of a prior art LCD. FIG. 2A is a plan view of the LCD of FIG. 1 showing a pixel array layout, and FIG. 2b is an equivalent circuit diagram of the pixel array layout of FIG. 2A.
As shown in FIGS. 1, 2a, and 2b, the prior art LCD includes a plurality of gate lines Gi, including a first to a fourth gate lines Gn to Gn+3, and a plurality of data lines Di, including a first to a fourth data lines Dn to Dn+3 a pixel electrode 11, a storage electrode 12, a TFT 13, a data driver 14, and a gate driver 15.
This configuration decreases the number of data driver channels by one third compared to a commercially available pixel array layout wherein the data line is a column line, which extends in a column direction, by using the data line Di as row line and removing gate driver integrated circuits (“IC”s) by directly integrating the gate driver 15 on a glass substrate, in a pixel array manufacturing process, to reduce manufacturing cost.
As shown in FIGS. 2a and 2b, two data lines, the first and the second data lines Dn and Dn+1 are disposed in one row pixel stripe 16, and one gate line, the first gate line Gn, is disposed in one column pixel stripe 17. The gate lines Gi are electrically connected in pairs and TFTs 13 are disposed in a zigzag fashion and are electrically connected to a corresponding data line Di and gate line Gi. Therefore, a data signal can be simultaneously applied to two pixel electrodes in two corresponding column pixel stripes and sufficient pixel charging time can be provided.
In the addition, to prevent a texture, which can be caused by a gate field and which may cause distortion, the storage electrode 12 can be disposed in close proximity to the gate line Gi.
In this configuration, however, because the gate line Gi is disposed in every column pixel stripe 17, and storage electrode 12 is disposed in close proximity to the gate line Gi, the aperture ratio is reduced. Furthermore, since two gate lines are electrically connected to one output terminal of the gate driver 15, a load of a gate line Gi can be relatively high so that a size of gate driver 15 may be increased. Therefore, a glass substrate use efficiency and a panel design margin can be reduced.